(1) Field of the Invention
The present invention relates to a processor such as a DSP and CPU, and more particularly to a processor that executes SIMD instructions.
(2) Description of the Related Art
Pentium®/Pentium® III/Pentium 4® MMX/SSE/SSE2 and others of the Intel Corporation of the United States are some of the existing processors that support SIMD (Single Instruction Multiple Data) instructions.
For example, MMX is capable of performing the same operations in one instruction on a maximum of eight integers stored in a 64-bit MMX register.
However, such existing processors have many limitations concerning the positions of operands on which SIMD operations are performed.
For example, when an existing processor executes a SIMD add instruction on the first register and the second register as its operands, with values A and B respectively stored in the higher bits and the lower bits of the first register and values C and D respectively stored in the higher bits and the lower bits of the second register, the resulting values are A+C and B+D. In other words, such added values are obtained as a result of adding data stored in the higher bits of the respective registers and as a result of adding data stored in the lower bits of the respective registers, meaning that an operand depends uniquely on the position in a register where data is stored.
Therefore, in order to obtain an added value A+D and an added value B+C targeting at the aforementioned first and second registers, the storage positions of data stored in the higher bits and data stored in the lower bits in either of the registers need to be exchanged before a SIMD add instruction is executed, or an ordinary SISD (Single Instruction Single Data) add instruction needs to be executed twice instead of using a SIMD add instruction.
Meanwhile, with the recent digitization of communications, it is necessary, in the fields of image processing and sound processing requiring digital signal processing (e.g. Fourier transform and filter processing), to perform the same operations on a plurality of data elements, but many cases require such processing as one for performing the same operations on a plurality of data elements located at a symmetric position with respect to the center of the data array. In such a case, two types of operands need to be sorted in reverse order, and the operation shall be performed on data stored in the higher bits of one of two registers and data stored in the lower bits of the other register, for example.
However, there is a problem in that a SIMD operation performed by the existing processors requires operands to be placed in the same order as each other in respective data arrays as mentioned above, which necessitates the reordering and the like of the operands as well as consuming a substantial time for digital signal processing.